1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory circuit and a memory device including the same.
2. Description of the Related Art
With the rapid increase in Integration degree of a memory device, tens of millions of memory cells are included in one memory device. When a fall occurs in any one of the memory cells, the corresponding memory device may not perform a desired operation. However, when a memory device is discarded as a defective product due to a fall occurring in a few memory cells, it is very inefficient in terms of the yield of products. The memory cell refers to a minimum unit that performs the unique function of the memory device. For example, the memory cell may indicate a unit cell for storing one-bit data.
Thus, in order to solve the above-described problem, a variety of methods have been attempted. For example, the variety of methods may include a method which can save a memory device using memory cells which are previously installed therein (hereafter, referred to as redundancy cells), even though a fail occurs in partial memory cells of the memory device. According to this method, a repair operation using redundancy cells is performed by replacing defective memory cells with redundancy cells in a row/column basis, using a redundancy row and a redundancy column which are previously installed in each cell block with a predetermined size.
FIG. 1 is a diagram illustrating a row repair operation of a memory device.
Referring to FIG. 1, the memory device may include a memory bank 110 and a plurality of fuse sets FS0 to FS15.
The memory bank 110 may be divided into first and second cell blocks 111 and 112. The first and second cell blocks 111 and 112 may include the plurality of word lines WL0 to WL511 and WL512 to WL1023 and a plurality of redundancy word lines RWL0 to RWL7 and RWL8 to RWL15, respectively.
Each of the fuse sets FS0 to FS15 may correspond to one of the redundancy word lines RWL0 to RWL15, and store the address of a word line which is repaired with the corresponding redundancy word line, among the word lines WL0 to WL1023. Hereafter, the address of the repaired word line will be referred to as repair address.
Since the memory bank 110 and the plurality of fuse sets FS0 to FS15 are remote from each other in the memory device, the memory device may sequentially transmit the repair addresses stored in the fuse sets FS0 to FS15 to latch sets (not illustrated in FIG. 1) which are positioned adjacent to the memory bank 110, and perform a repair operation using the transmitted repair addresses. The repair operation may indicate an operation of replacing a word line corresponding to a repair address with a redundancy word line.
Up to now, in existing devices, the redundancy word lines RWL0 to RWL7 corresponding to the fuse sets FS0 to FS7 are configured to repair only the word lines WL0 to WL511 of the first cell block 111 and the redundancy word lines RWL8 to RWL15 corresponding to the fuse sets FS8 to FS15 are configured to repair only the word lines WL512 to WL1023 of the second cell block 112. This e may lead to an inefficiency. When, for example, nine defective word lines occur only in the first cell block 111 of the memory bank 110, although the redundancy word lines RWL8 to RWL15 of the second cell block 112 are not yet used, the redundancy word lines RWL0 to RWL7 of the first cell block 111 cannot repair all of the nine defective word lines. Thus, the memory device is inevitably discarded as a defective product.